This disclosure relates to an output device that outputs a data signal in synchronization with a clock signal.
An example of an output device that outputs a data signal in synchronization with a clock signal is the one having the configuration illustrated in FIG. 8. An output device 120 illustrated in FIG. 8 includes an output buffer 124 and a driving unit 122 that drives the output buffer 124. The driving unit 122 includes a flip-flop 126 and driving circuits that shape a waveform of a driving signal supplied from the flip-flop 126 and output the signal. In the example shown in FIG. 8, inverters 128A and 128B are used as the driving circuits.
Although not illustrated, the output buffer 124 operates using a power supply that supplies an upper-limit output voltage and a lower-limit output voltage. While the driving unit 122 operates using a power supply different from that used by the output buffer 124. That is, the flip-flop 126 and the driving circuits 128A and 128B in the driving unit 122 operate with the same power supply.
As illustrated in FIG. 9, a data signal is sampled and held in the flip-flop 126 in the driving unit 122 in synchronization with a rise of the clock signal and output to a node A. The data signal output to the node A is inverted by the driving circuits 128A and 128B, and the inverted signals are output as driving signals. The driving signal is input into gate of each of a PMOS (P-channel metal-oxide semiconductor (MOS) transistor) 130A and an NMOS (n-channel MOS transistor) 130B.
When the data signal is H level, the data signal output from the flip-flop 126 is H. The H level is inverted to L level by the driving circuits 128A and 128B, and the PMOS 130A is turned on and the NMOS 130B is turned off in the output buffer 124. Accordingly, the output terminal is connected to the upper-limit output voltage, and the output signal level becomes H. In contrast, when the data signal is L, the output signal is connected to the lower-limit output voltage, and the level becomes L.
As illustrated in the timing chart in FIG. 9, an amount of current flows from the power supply to the driving unit varies dependent on whether the level of the data signal changes. The amount also depends on whether the data signal makes a L-to-H transition or a H-to-L transition.
In the example illustrated in FIG. 9, the current consumed by the driving unit has peaks at the rising edges of the clock signal. Specifically, the current has the largest peak when the data signal output to the node A changes from L to H, the second largest peak when the data signal output to the node A changes from H to L, and the smallest peak when the data signal does not change.
In this way, the amount of current consumed by the driving unit 122 varies dependent on the level of the data signal output to the node A. Accordingly, different amounts of noises, or fluctuations in the voltage, of the power supply are generated dependent on the data signal output to the node A. As a result, jitter, or timing fluctuation, in the output signal increases. This is a serious problem in particular for example when a plurality of output devices 120 operates using the same power supply.
In an output device 132 illustrated in FIG. 10, the voltage of the power supply used by the driving unit 122 and that used by the output buffer 124 are different. Accordingly, level shifters (L/S) 134A and 134B are added before the flip-flop 126 in the output device 120 illustrated in FIG. 8. In the output device 132, voltage levels of the data signal and that of the clock signal are shifted by the level shifters 134A and 134B such that the voltage levels of the data and clock signals match with the voltage of the power supply used by the output buffer 124.
When the voltage of the power supply used by the output buffer 124 is higher than that of the driving unit 122, because the flip-flop 126 and the driving circuits 128A and 128B operate at the voltage of the power supply used by the output buffer 124, the current consumption may increase. As a result, the power-supply noise may increase, and jitter in the output voltage signal may be larger than that in the output device 120 illustrated in FIG. 8.
One example of the prior art for solving the problem of power supply noise described above is illustrated in Japanese Unexamined Patent Application Publication No. 2005-318264 (patent literature). As illustrated in FIG. 11, an output device 146 illustrated in this patent literature includes a cancel data generating circuit 148, a dummy output buffer 150A, and an output buffer 150B.
As illustrated in the timing chart in FIG. 12, a data signal changes in synchronization with a clock signal in the output device 146, and the data signal is output from the output buffer 150B. The cancel data generating circuit 148 generates a cancel data signal that changes in synchronization with rising edges of the clock signal when the data signal does not change, and the cancel data signal is output from the dummy output buffer 150A.
As illustrated in the timing chart in FIG. 12, a current flows in the output buffer 150B when the data signal changes in synchronization with the rising edge of the clock signal. The same amount of current flows in the dummy output buffer 150A when the cancel data signal changes, i.e., when the data signal does not change, in synchronization with the rising edge of the clock signal. Accordingly, the output device 146 as a whole consumes the same current in synchronization with every rising edge of the clock signal.
That is, in the output device 146 described in the above-mentioned patent literature, the cancel data generating circuit enables to consume, at the rising edges of the clock signal when the data signal does not change, the same amount of current as the amount current consumed when the data signal changes. Thereby, it is achieved that the amounts of current consumed by the output device as a whole does not depend on whether the data signal changes or does not change. This technique can reduce the jitter in the output voltage signal.
However, this technique increases the circuit scale because the cancel data generating circuit 148 and the dummy output buffer 150A are necessary. In addition, noises in the power supply that the cancel data generating circuit 148 generates may be a problem.